Buy BGA Rework Station

    

1.Application Of Automatic Optical BGA Rework Station

Work with all kinds of motherboards or PCBA.

Solder, reball, desoldering different kind of chips: BGA,PGA,POP,BQFP,QFN,SOT223,PLCC,TQFP,TDFN,TSOP,

PBGA,CPGA,LED chip.

DH-G620 is totally same as DH-A2, automatically desoldering, pick-up, puting back and soldering for a chip, with optical alignment for mounting,no matter whether you have experience or not, you can master it in one hour.

3.Specification of Automatic Optical BGA Rework Station 

power	5300W
Top heater	Hot air 1200W
Bottom heater	Hot air 1200W.Infrared 2700W
Power supply	AC220V±10% 50/60Hz
Dimension	L530*W670*H790 mm
Positioning	V-groove PCB support, and with external universal fixture
Temperature control	K type thermocouple, closed loop control, independent heating
Temperature accuracy	±2℃
PCB size	Max 450*490 mm,Min 22*22 mm
Workbench fine-tuning	±15mm forward/backward,±15mm right/left
BGAchip	80*80-1*1mm
Minimum chip spacing	0.15mm
Temp Sensor	1(optional)
Net weight	70kg

 

4.Why Choose Our Automatic Optical BGA Rework Station? 

 

5.Certificate 

UL, E-MARK, CCC, FCC, CE ROHS certificates. Meanwhile, to improve and perfect the quality system, 

Dinghua has passed ISO, GMP, FCCA, C-TPAT on-site audit certification.

 

6.Packing & Shipment

 

 

7.Shipment for Automatic Optical Reballing BGA Machine

DHL/TNT/FEDEX. If you want other shipping term, please tell us. We will support you.

Bank transfer, Western Union, Credit Card.

Please tell us if you need other support. 

8. How DH-A2 Automatic BGA IC Reballing Machine work?

 

 

9. Related knowledge

About Flash Chip

Supply Dynamics

Recently, SandForce's new parent company, LSI, announced that they are developing new firmware for SF master SSDs in Ultrabooks. The primary function of this firmware is to reduce the power consumption of the SSD, improve its performance, and accelerate the startup speed.

Parameters

• 3.3V power supply
• The internal memory cell array of the chip is (256M + 8.192M) bits × 8 bits, with data registers and buffer memory both being (2k + 64) bits × 8 bits.
• I/O port with instruction/address/data multiplexing
• Program and erase commands can be suspended during power conversion
• Thanks to reliable CMOS moving gate technology, the chip can achieve a maximum of 100k program/erase cycles, ensuring data storage for 10 years without loss.

Working Status

• I/O0–I/O7: Data input and output ports, typically used for inputting instructions and addresses and for input/output of data. Data is input during the reading process. When the chip is not selected or cannot output data, the I/O ports are in a high-impedance state.
• CLE: Instruction latch, used to activate the instruction to the instruction register path and latch the instruction on the rising edge of WE when CLE is high.
• ALE: Address latch, used to activate the path of the address to the internal address register, and the address is latched on the rising edge of WE when ALE is high.
• CE: Chip Enable, used to control device selection. When the device is busy, CE is high and ignored, preventing the device from returning to the standby state.
• RE: Read Enable, used to control the continuous output of data to the I/O bus. The output data is valid only on the falling edge of RE, and it can also accumulate internal data addresses.
• WE: Write Enable terminal, used to control the instruction writing to the I/O port. The command, address, and data can be latched on the rising edge of the WE pulse through this port.
• WP: Write Protect, which can prevent writing during power conversion via the WP terminal. When WP is low, the internal high-level generator will be reset.
• R/B: Ready/Busy output. When R/B is low, it indicates that a program, erase, or random read operation is in progress. After the operation is completed, R/B will return to high. Since the terminal is an open-drain output, it will not be in a high-impedance state even when the chip is not selected or output is disabled.
• PRE: Power-on Read operation, used to control automatic read operation when power is on. The PRE terminal can be connected to VCC to enable automatic read on power-up.
• VCC: Chip power terminal.
• VSS: Chip ground.
• NC: Not connected (floating).

Work Status Editing

1.Page Read Operation

The default state of the flash chip is the read state. To initiate a read operation, the 00h address is written to the instruction register via four address cycles. Once the instruction is latched, the read operation cannot be written to the next page. Data can be randomly output from one page by issuing a random data output instruction. The data address can automatically increment to the next address via the random output instruction. Random data output operations can be repeated.

2.Page Programming

Flash chip programming is performed page-by-page, but it supports multiple partial page programming within a single page programming cycle. The maximum number of consecutive pages for partial page programming is 2112. The programming operation can be initiated by writing the page program acknowledgment instruction (10h), but continuous data must be input before the instruction (10h) is written. After writing a continuous data input instruction (80h), four address cycles and data loading will follow, but if the word differs from the programmed data, no data needs to be loaded. The chip supports random data input within the page and can automatically adjust the address according to the random data input command (85h). Random data entry can also be repeated.

3.Cache Programming

Cache programming is a form of page programming that can be performed by a 2112-byte data register and is valid for one block only. Since the flash chip has a page buffer, continuous data input can occur while the data register is being programmed into memory cells. Cache programming can only begin after an incomplete programming cycle ends, with the data registers passed from the cache. Internal programming can be monitored by the R/B pin. If the system uses only the R/B pin to track programming progress, the final page of the target program must be scheduled in the current page programming instructions.

4.Storage Unit Dubbing

This process allows quick and efficient overwriting of data in a page without accessing external memory. By shortening the time spent on continuous access and reloading, system execution performance is improved. This is especially advantageous when part of a block is upgraded, and the rest of the block needs to be copied into a new block. The operation uses a continuous read command, but without continuous access or copying from the destination address. A read operation of the original page address instruction "35h" will transfer the entire 2112 bytes of data to the internal data buffer. Once the chip returns to the ready state, the page copy data input instruction with the destination address loop is written. The error status in this operation is indicated by the "pass/fail" flag. If the operation takes too long, bit operation errors may occur due to data loss, resulting in an external error check failure. In such cases, the operation should be corrected with two error checks.

5.Block Erase

The erase operation of the flash chip is performed on a block basis. The block address load starts with a block erase instruction and is completed in two cycles. In practice, when address lines A12 to A17 are left floating, only address lines A18 to A28 are available. The erase operation begins by loading the erase confirmation command and the block address. This sequence must be followed to prevent external noise from affecting the memory and causing an erase error.

6.Read Status

The status register within the flash chip confirms the completion of program and erase operations. After writing the instruction (70h) to the instruction register, the read cycle outputs the contents of the status register to the I/O pins on the falling edge of CE or RE. The instruction register will remain in the read state until a new instruction arrives. Therefore, if the status register is being read during a random read cycle, a read instruction should be issued before the read cycle begins.